Applying Partial Fault Tolerance with Explicit Area Constraints

Document Type

Article

Publication Date

1-1-2013

Publication Title

International Journal of Embedded Systems

Abstract

As field programmable gate arrays find increasing use in aerospace and terrestrial applications, a number of methods of fault tolerance have been developed to ensure reliable operation. Current techniques output the required circuit area based on the desired level of fault tolerance with some techniques increasing the area by over 200%. In deployed systems, however, the FPGA is fixed and the area available for adding fault tolerance is limited. As a consequence, protecting an updated, larger circuit using the same fault tolerance scheme may result in a design that no longer fits in the deployed FPGA. This situation dictates the need for a technique that can trade fault tolerance for lower area penalties. To fill this need, this paper presents a new area constrained approach which accepts available hardware resources as an input and outputs a maximally fault tolerant circuit.

Volume

5

Issue

1/2

First Page

67

Last Page

80

DOI

DOI: 10.1504/IJES.2013.052145

ISSN

1741-1068

Comments

ESSN: 1741-1076

Rights

© 2013 Inderscience

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