Title
An ASIC Design of a Novel Pipelined and Parallel Sorting Accelerator for a Multiprocessor-on-a-chip
Document Type
Conference Proceeding
Publication Date
4-3-2006
Publication Title
IEEE Xplore
Conference Name
2005 6th International Conference on ASIC
Abstract
We introduce a pipelined and parallel sorting algorithm, with the time, logic, and memory complexity of O(n), O(radicn) and O(n), respectively. We then model, verify, and synthesize this unconditional algorithm for 4k-word clusters as an ASIC accelerating, plug-in engine tailored to MaRS, a multiprocessor-on-a-chip that we have recently developed; so that this engine may replace any of the processing elements (PEs) in MaRS, and provide the other PEs with an efficient sort function, using the same network protocol based on which inter-PE communication is carried out
Rights Statement
© 2006 IEEE
Recommended Citation
Tabrizi, Nozar and Bagherzadeh, Nader, "An ASIC Design of a Novel Pipelined and Parallel Sorting Accelerator for a Multiprocessor-on-a-chip" (2006). Electrical & Computer Engineering Presentations And Conference Materials. 17.
https://digitalcommons.kettering.edu/electricalcomp_eng_conference/17
Comments
https://doi.org/10.1109/ICASIC.2005.1611246