Title

Specification and Verification of Pipelining in the ARM2 RISC Microprocessor

Document Type

Article

Publication Date

10-1998

Publication Title

ACM Transactions on Design Automation of Electronic Systems

Abstract

Gurevich Abstract State Machines (ASMs) provide a sound mathematical basis for the specification and verification of systems. An application of the ASM methodology to the verification of a pipelined microprocessor (an ARM2 implementation) is described. Both the sequential execution model and final pipelined model are formalized using ASMs. A series of intermediate models are introduced that gradually expose the complications of pipelining. The first intermediate model is proven equivalent to the sequential model in the absence of structural, control, and data hazards. In the following steps, these simplifying assumptions are lifted one by one, and the original proof is refined to establish the equivalence of each intermediate model with the sequential model, leading ultimately to a full proof of equivalence of the sequential and pipelined models.

Volume

3

Issue

4

First Page

563

Last Page

580

DOI

10.1145/296333.296345

ISSN

ISSN: 1084-4309, ESSN: 1557-7309

Rights

© 1999 ACM

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