A Parallel Sort Engine with Dynamic Memory for a Multiprocessor-on-a-Chip
Proceedings of the Fourth IASTED International Conference on Circuits, Signals, and Systems (CSS) 2006
We propose a custom-designe d alternative to a memory system (generated by a memory generator) used in a 4K-word sorting accelerator which improves area efficiency by some 20%. We also show how the control unit is dramatically simplified with this n ew memory comparing with the sophisticated memory controller in the previous version. Furthermore, s ince the memory introduced here is custom designed, its size is tailored to any specific need.
© 2006 ACTA Press
Tabrizi, Nozar and Bagherzadeh, Nader, "A Parallel Sort Engine with Dynamic Memory for a Multiprocessor-on-a-Chip" (2006). Electrical & Computer Engineering Publications. 14.