Maximizing Area-constrained Partial Fault Tolerance in Reconfigurable Logic

Document Type

Conference Proceeding

Publication Date


Publication Title

Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays

Conference Name

FPGA '10: Proceedings of the 18th Annual ACM/SIGDA


As field programmable gate arrays find increasing use in aerospace and terrestrial applications, a number of methods of fault tolerance have been developed to ensure reliable operation. Most current techniques output the required circuit area based on the desired level of fault tolerance with some techniques increasing the area by over 200%. In deployed systems, however, the FPGA is fixed and the area available for adding fault tolerance is limited. As a consequence, protecting an updated, larger circuit using the same fault tolerance scheme may result in a design that no longer fits in the deployed FPGA. This situation dictates the need for techniques that can trade fault tolerance for lower area penalties. Area constrained approaches accept available hardware resources as an input and outputs a partially fault tolerant circuit. The open question with these approaches is selecting the circuit subset to protect which will maximize the fault coverage. This paper presents several methodologies for selecting subsets and analyzes their performances on several circuits based on fault coverage provided and additional delay.



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